1. Field of the Invention
This invention relates generally to semiconductor fabrication technology, and, more particularly, to a method for semiconductor fabrication supervision and optimization.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the quality, reliability and throughput of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for higher quality computers and electronic devices that operate more reliably. These demands have resulted in a continual improvement in the manufacture of semiconductor devices, e.g., transistors, as well as in the manufacture of integrated circuit devices incorporating such transistors. Additionally, reducing defects in the manufacture of the components of a typical transistor also lowers the overall cost per transistor as well as the cost of integrated circuit devices incorporating such transistors.
The technologies underlying semiconductor processing tools have attracted increased attention over the last several years, resulting in substantial refinements. However, despite the advances made in this area, many of the processing tools that are currently commercially available suffer certain deficiencies. In particular, such tools often lack advanced process data monitoring capabilities, such as the ability to provide historical parametric data in a user-friendly format, as well as event logging, real-time graphical display of both current processing parameters and the processing parameters of the entire run, and remote, i.e., local site and worldwide, monitoring. These deficiencies can engender nonoptimal control of critical processing parameters, such as throughput accuracy, stability and repeatability, processing temperatures, mechanical tool parameters, and the like. This variability manifests itself as within-run disparities, run-to-run disparities and tool-to-tool disparities that can propagate into deviations in product quality and performance, whereas an improved monitoring and diagnostics system for such tools would provide a means of monitoring this variability, as well as providing means for optimizing control of critical parameters.
Among the parameters it would be useful to monitor and control are photolithography overlay measurements. Measurements of photolithography overlay are facilitated by using overlay target structures, as shown in FIGS. 3-8, for example. These photolithography overlay target structures are formed on the surface of a workpiece (such as a semiconducting wafer) so that successive portions of the overlay target structures are formed as each successive process layer is formed and patterned, using a photolithography masking step, above the surface of the workpiece. The positional relationship of the photolithography pattern of one process layer to the photolithography pattern of another process layer determines the quality of the photolithography pattern alignment. Accurate measurement of this photolithography overlay is important in semiconductor manufacturing.
However, accurate measurement of this photolithography overlay using photolithography overlay target structures can typically be inhibited by damage to the photolithography overlay target structures induced by chemical-mechanical planarization (CMP). Chemical-mechanical planarization (CMP) is a process designed to remove and/or eliminate unwanted surface or xe2x80x9ctopographicxe2x80x9d features of a process layer. Chemical-mechanical planarization (CMP) typically involves physically polishing the surface or xe2x80x9ctopographyxe2x80x9d of a process layer in the presence of a chemically reactive slurry to remove and/or eliminate the unwanted surface or topographic features of the process layer. Needless to say, chemical-mechanical planarization (CMP) typically disturbs and/or damages those portions of the photolithography overlay target structures that may be present in the process layer being subjected to the chemical-mechanical planarization (CMP). This disturbance and/or damage to those portions of the photolithography overlay target structures typically inhibits the accurate measurement of the photolithography overlay taken using the disturbed and/or damaged photolithography overlay target structures.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
In one aspect of the present invention, a method is provided, the method comprising processing a workpiece, having a photolithography overlay target structure disposed thereon, using a chemical-mechanical planarization (CMP) tool and measuring a photolithography overlay parameter using the photolithography overlay target structure. The method also comprises forming an output signal corresponding to the photolithography overlay parameter measured and to the chemical-mechanical planarization (CMP) tool used and using the output signal to improve at least one of accuracy in photolithography overlay metrology and fault detection in chemical-mechanical planarization (CMP).
In another aspect of the present invention, a computer-readable, program storage device is provided, encoded with instructions that, when executed by a computer, perform a method, the method comprising processing a workpiece, having a photolithography overlay target structure disposed thereon, using a chemical-mechanical planarization (CMP) tool and measuring a photolithography overlay parameter using the photolithography overlay target structure. The method also comprises forming an output signal corresponding to the photolithography overlay parameter measured and to the chemical-mechanical planarization (CMP) tool used and using the output signal to improve at least one of accuracy in photolithography overlay metrology and fault detection in chemical-mechanical planarization (CMP).
In yet another aspect of the present invention, a computer programmed to perform a method is provided, the method comprising processing a workpiece, having a photolithography overlay target structure disposed thereon, using a chemical-mechanical planarization (CMP) tool and measuring a photolithography overlay parameter using the photolithography overlay target structure. The method also comprises forming an output signal corresponding to the photolithography overlay parameter measured and to the chemical-mechanical planarization (CMP) tool used and using the output signal to improve at least one of accuracy in photolithography overlay metrology and fault detection in chemical-mechanical planarization (CMP).